View HA13609ANT_141111.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HA13609ANT
Three-Phase Brushless Motor Driver
ADE-207-232 (Z) 1st. Edition May 1997 Description
The HA13609ANT is a 3-phase brushless motor driver IC with digital speed control. It is designed for use as a PPC or LBP scanner motor driver and provides the functions and features listed below.
Function
* * * * * * * * * * * * * * * Power MOS and power bipolar transistor driver circuits 16-bit serial interface Variable-speed digital speed control circuit Digital PLL Digital ready circuit PWM oscillator circuit Charge pump circuit Integrating amplifier circuit Current limit circuit Overshoot prevention circuit Braking function (with braking compete signal) Forward/reverse direction circuit Hall open circuit protection Watchdog timer (LVI, POR, and RST outputs) Stuck rotor protection
Features
* * * * * * * * High breakdown voltage (50V/30mA) power transistor drive circuit PWM drive Variable speed control is possible (varying the servo filter constants is not required) Selectable rotation control method (discriminator control, PLL plus discriminator control) Selectable feedback type (voltage or current) Allows both PWM frequency switching and 100% duty operation Selectable current limiting level Braking mode selection (reverse braking, regeneration braking)
HA13609ANT
Block Diagram
VSS (5 V) C101 VSS VPS C102 VSS = Bip use 10 to 50 V= MOS use
21
R101 Hall amplifier
25
U U V Matrix V W W FH x 3 Overshoot preven- OSI tion Duty 100 - 40 k - + MASK MOTOR ON BRAKE (2 bit) DUTY 100 READY O.S.I ON VRef (2 bit) MASK CONTROL RWD/FWD D1 (2 bit) D2 (2 bit) PLL SEL OR Icp, PC ON VP (3 bit) fPWM (2 bit) MODE SEL D1 Current sense - + VSS MASK Error amp
42
Hu
U+ U- V+ V- W+ W-
+ - + - + - Open circuit protection R/F RWD/FWD 1.25 V
36 (Open collector) 35 (Push-pull) 34 33 32 31
41 40
Hv
39 38
Hw
37
VSS R102 R126
20
R127
PWM OSC fPWM
12
C106
22
C108 RST 8 Monitor output 7 (Ready: Low) DATA OUT 4 CLK 1 fMAX = 8 MHz ENABLE 2 DATA 3
P.O.R
L.V.I
BRAKE
BRAKE
No/8 Counter
+ PWM comp.
27 Current feedback input 17 Error amplifier input
26
R106
24
VRef VRef
18
1.1 V - +
R107
Serial port (16 bits) FH x 3
Stuck rotor protector PC
Buffer
23
C105
Rotation monitor output 6
Precharge
16
C3
VSS
1.4 V
29
MR
28
+ AMP -
Waveform shaping
Ready
D1
Ready 4, 8%
Integral -+ CONT. Icp x 2
R3
15
R7
SPEED CLK 5 (0.2 to 5 kHz)
D2
Programmable discriminator (1024 to 4095) PLL Discriminator
Charge pump
9
OSC
D2
19
R1 Vp Vp
10
1M
11
30
13
14
R4 R6
20 p
8 MHz MAX
20 p R5
C4
2
HA13609ANT
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name CLK ENABLE DATA DATA OUT SPEED CLK TACHO OUT READY RST OSC IN OSC OUT S-GND PWM OSC PLL OUT DIS OUT INTEG IN CP OUT ERROR AMP IN BUFFER OUT R1 LVI VSS POR LOCK PRO VRef VPS C Sense CFB MR IN - MR IN + P-GND Function Serial port reference signal input Serial port data write/latch signal input Serial port data input Serial port data transfer complete signal output Speed command signal input Rotation monitor (MR, Hall x3) output Ready and braking done (no/8) output (open collector output) Power supply (V SS ) monitor output. High when a reduced power-supply voltage is detected. Oscillator circuit input. Reference signal for all circuits other than the serial port. Oscillator circuit output Small-signal ground Connection for the capacitor that sets the oscillator frequency. SPEED CLK vs. speed detection signal speed comparison output SPEED CLK vs. speed detection signal phase comparison output Integrating amplifier input Charge pump and integrating amplifier output Error amplifier input Buffer amplifier output. Connect to pin 17 when current feedback is selected. Charge pump output current and PWM oscillator frequency setting Reduced voltage detection level setting Small-signal circuit power supply. 5.5V maximum Power-on reset delay time setting Motor rotation constraint mode coil current on/off time setting Current limit setting Output driver power supply. 50V maximum Motor coil current detection Current feedback input Speed detection input Speed detection input Output driver ground
3
HA13609ANT
Pin Functions (cont)
Pin No. 31, 33, 35 32, 34, 36 37 to 42 Pin Name U, V, W U, V, W U+, U- V+, V- W+, W- Function Lower arm driver push-pull output. Driven by a PWM signal. (Connect power NMOS or NPN transistors.) Upper arm driver open drain output. (Connect a power PMOS or PNP transistor.) Hall signal inputs
4
HA13609ANT
Serial Port Input Data Structure
MSB A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0
Dummy
A0 = 1
Mode control
Dummy
A0 = 0
Data control
DATA OUT DATA CLK ENABLE Serial port (16 bits) A0 Decoder Mode control register (11 bits) A0 = 1 Data control register (11 bits) A0 = 0 Mode control
Data control
Mode Control Register (A0 = 1)
Bit MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 Symbol MOTOR ON BRAKE 1 BRAKE 2 DUTY 100 READY O.S.I ON VRef 1 VRef 2 MASK CONTROL R/F MOTOR ON MD1 MD2 1 MOTOR OFF 1 0 1 0 1 1 Brake Brake Brake BRAKE OFF 1 2 3 DUTY 100% DUTY 0 0 4% Active MD6 MD7 VRef x2 Discriminator Reverse 0 0 VRef x2 1 0 x1 0 1 x0.75 8% Non Active 1 1 x0.5 x1 Discriminator + PLL Forward 0 *1
*2
*3
5
HA13609ANT
Data Select Register (A0 = 0)
Bit DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 D1 A D1 B D2 A D2 B PLLSEL1 OR Icp Symbol DD0 DD1 D1 DD2 DD3 D2 1 0 0 1/1 0 0 1/1 0 0 1 0 1/2 1 0 1/2 0 1 1/4 0 1 1/4 1 1 1/8 1 1 1/8 *4 0
DD4 DD5 PLLSEL2 OR PC ON PLL OUT(Vp-p) VP1 VP2 VP3 fPWM1 fPWM2 DD6 DD7 DD8 VP (V) DD9 DD10 fPWM
1 0 1 1 1 0 x100% x75% x50% x25% 0 0 0 1 0 1 0 0 1 0 0 0 2.2 0 0 fPWM x1 +0.15 1 0 x1.4 +0.3 0 1 x1.9 +0.45 1 1 x2.8
1 1 0 +0.6
1 0 1 -0.15
0 1 1 -0.3
1 1 1 -0.45
*5
*6
Notes: 1. Off: The brake function does not operate. Brake 1: Braking up to No/8. Brake 2: Braking up to No/8, and then regenerative braking. Brake 3: Regenerative braking. The No/8 signal is output. During a braking operation, when the MR frequency when braking completes cannot be detected in the circuit (During braking, the speed detection signal for under setting is not output over the 2/D1 occurrence. Thus this occurs more easily for lower settings.), reverse rotation may continue in some cases. Note that this bit is also used to set the rotation monitor output (FH x 3 or the MR frequency). FH x 3 is only output from the rotation monitor when motor on (MD0 = 1) and brake 3 are selected. 2. The ready setting range has the following manufacturing variation: 4.3% 25% (@MD4 = 1) 8.6% 25% (@MD4 = 0) 3. This function masks the current limiter input (pin 27) (incorrect operation due to the recovery current). See page 20 for details. 4. The PLL output setting indicates a change relative to 3.5 Vp-p. See the electrical characteristics. This is valid when MD9 = 0 (PLL control). Note that DD4 also functions as the Icp selection in discriminator control mode. VR1 Icp = 4 * R1 DD4 = 1 . . . . . Icp x 2 @MD9 = 1 DD4 = 0 . . . . . Icp x 1
6
HA13609ANT
DD5 also controls the PC on function to reduce motor rotation overshoot when MD9 is 1 (discriminator control). This function does not operate when D9 is 0. The precharge voltage (i.e., the integrator output voltage initial clamp voltage) can be set by Vp1 to Vp3 (DD6 to DD8). The figure shows the precharge operation. MD0 or MD10 NO Integrator output Vp 0V Precharge 5. The Vp setting indicates the change relative to 2.2V. See the electrical characteristics. 6. Indicates the change relative to f PWM. See the setting formula. Ready lock range (MD4)
7
HA13609ANT
Timing Chart (Forward Mode)
Hu Hv Hw
+ Hall amplifier input 0 -
Vhys
VOH1 U output VOL VOH1 V output VOL VOH1 W output VOL VOH U output VOL VOH V output VOL VOH W output VOL PWM PWM PWM PWM PWM PWM
8
HA13609ANT
Serial Port Timing Chart
tr, tf < 20 nsec, tsu, th > 20 nsec The tr and tf times are stipulated tw > 40 nsec at 10% and 90%, respectively. th ENABLE tsu th 50% tsu CLK tw DATA tsu DATA OUT td1 50 nsec td2 50 nsec A4 th tw A3 tsu D1 D0 tsu 50% 50% 50%
Braking Function
Input and Output Logic
Serial Port Input MOTOR ON (MD0) 1 BRAKE 1 (MD1) * * 0 0 * * BRAKE 2 (MD2) * * 0 * * R/F (DD10) 0 1 * 0 1 Output Rotation Direction Forward Reverse -- Reverse Forward Braking OFF OFF OFF Brake *2 *3 *1
Notes: 1. OFF: The braking function does not operate. 2. The IC goes to standby mode. 3. See the description of mode control for details on the braking operation.
9
HA13609ANT
N1 Forward 0 Braking set Braking or regeneration braking
Reverse Regeneration braking N2
MDO (MOTOR ON)
MD10 (R/F) *3 tset up Rotation monitor output set Braking set *3 thold SPEED CLK input Monitor output (open drain) N1 N2 *2 *1 *3 tset up N1 Rotation monitor output set
MD1 (BRAKE1) to MD2 (BRAKE2)
Ready
Ready
*4 No/8 detection
Ready
Notes: 1. The IC goes to standby mode when MOTOR ON, BRAKE1, and BRAKE2 are all 0. 2. Hold the data values here. 3. thold, tset up > 1 x4 fSPEED CLK
4. The No/8 (braking completion) function does not operate when BRAKE1 and BRAKE2 are 0. Note that the No/8 detection signal is initialized to the high level in the mode in note 1 (standby mode).
10
HA13609ANT
Basic Application Circuit (Bipolar Transistor Circuit, Discriminator + PLL, Voltage Feedback, and Hall Elements)
VSS VPS
VSS 21 R101 Hu 42 U+ 41 U- Hv 40 V+ 39 V- Hw VSS R102 R126 20 LVI R127 22 P.O.R C108 8 RST 38 W+ 37 W- VSS 25 VPS
C101 R114 R108 U 36 R109 Q2 R117 R115 R110 V 34 R111 Q4 R118 R116 R112 W 32 R113 Q6 R119 R120 Current limiter 26 C107 C106 PWMOSC 12 R106 3 DATA 5 SPEED CLK VRef 24 C105 Lock protection 23 R107 RNF VSS Q5 D5 D6 Q3 D3 D4 Q1 D1 D2
U 35
V 33
W 31 7 Monitor output 4 DATA OUT MPU 1 CLK 2 ENABLE
VSS MR 29 MR IN+ 28 MR IN- Current feedback input 27
Error amplifier input 17 Buffer amplifier output 18 Rotation monitor 6 output Integrator output 16 9 OSC IN C3 Integrator input 15 19 PLL 11 30 13 Discriminator 14 R4 R6 C4 R5 R1 R7 R3
C103 X'tal C104 R105 10 OSC OUT
11
HA13609ANT
Application Circuits
Application Circuit 1 (Discriminator)
Error amplifier input 17 Buffer amplifier output 18 Integrator output 16 C3 Integrator input 15 Discriminator 14 19 R1 R2 C1
PLL 13
Application Circuit 2 (MOS Transistor Circuit)
VSS VPS
C101 21 VSS 25 VPS
C102 ZD1 R114 R108 U 36 R109 M2 R117 ZD2 R115 R110 V 34 R111 M4 R118 ZD3 R116 R112 W 32 R113 M6 R119 RNF M5 D5 D6 M3 D3 D4 M1 D1 D2
U 35
V 33
W 31
12
HA13609ANT
Application Circuit 3 (Current Feedback)
RNF R125 Current feedback input 27 R121 Error amplifier input 17 Buffer amplifier output 18 C110
Application Circuit 4 (Hall IC input)
VSS
R103 R104 VSS 21 R122 IC 42 U+ 41 U- R123 IC 40 V+ 39 V- R124 IC 38 W+ 37 W- VSS C101
Application Circuit 5 (External Reset Input)
VSS R126 20 LVI External reset input H: standby 22 P.O.R C108 8 RST
13
HA13609ANT
External Components
Part No. R101, R102 R103, R104 R105 R106, R107 R108 to R113 R114 to R119 R120 R121 R122 to R124 R125 R126, R127 RNF R1 R2 R3 to R7 C101, C102 C103, C104 C105 C106 C107 C108 C110 C111 to C113 C1 C2 C3, C4 ZD1 to ZD3 D1 to D6 X'tal Recommended Value -- -- 1M -- -- -- 4.7k -- -- -- -- -- 1.5k -- -- 0.1F 10p to 50pF -- -- -- -- -- -- -- -- -- 20V -- 4 to 8MHz Purpose Hall element bias current Hall IC applications, Hall input voltage Oscillator stabilization Current limiter reference voltage Power transistor base current limiter Power transistor base-emitter resistors (gate-source resistors) Current limiter filter Current feedback input filter Hall IC output current Current feedback input gain adjustment LVI operating voltage, external reset input pull up Current detection Integration constant, PWM carrier frequency Integration constant Integration constant Power supply stabilization Oscillator stabilization Lock protection operation time PWM carrier frequency Current limiter filter Power-on reset delay time Current feedback input filter Hall output stabilization Integration constant Integration constant Integrator filter MOS power transistor gate destruction protection Fly wheel diodes Oscillator 7 4 5 13 11 9 8 2 2 3 8 8 6, 7 15 16 16 13 9 14 10 11 1 2, 3, 5 2 3 Note 12 14
Notes: 1. Current limiter operates according to the following formula: V Iop = Ref [A] RNF Here, V Ref is the value according to the VRef select function.
14
HA13609ANT
2. Use the following formulas as a guideline for setting the integration constant (@MD9 = 1). To minimize rotation deviation, set R1 to a relatively small value. 2 o * f * D1 [rad/s] 20 MR R1 = 9.55 * VR1 * KT * R2 *A 4 * J * o * No []
However, R1 must be in the range 1.5k R1 15k. C1 = 1 / (10 * o * R2) C2 = 10 * C1 Here, No f MR D1 VR1 KT J A [F] [F]
: Rotation speed [min-1 ] : MR frequency [Hz] : Divider determined by D1 select : Charge pump bias voltage 1.16 [V] : Motor torque constant [N*m/A] : Motor moment of inertia [kg*m2] : PWM comparator current gain [A/V] 2Vps - 0.83VE - Vsat Voltage feedback method: A = Rm * Vosc Current feedback method: A = GB RNF
VPS : Power system power-supply voltage [V] VE : Motor back EMF [V P-P/T*T] Vsat : External transistor saturation voltage [V] (See the electrical characteristics) Rm : Motor coil resistance [/T*T] Vosc : PWM amplitude voltage [V P-P] (See the electrical characteristics) GB : Buffer amplifier gain [V/V] (See the electrical characteristics) 3. Use the following formulas as guidelines for setting the integrator filter: First determine the angular frequency of P for DIS OUT and PLL OUT. P = 2 * fMR * D1 [rad/s] Determine the angular frequency of M for Motor. 9.55 1 Vref * KT * - TL [rad/s] M No J RNF Determine the o. o = P * M [rad/s] Determine the integrator's DC gain G(E) . J * o 1 G(E) = * 9.55 * KT * A Z Ko * D1 * 2 * * PLL SEL o 60 Here, Ko : PLL gain = 0.28 TL : Rated load torque PLL SEL : PLL output ratio Vref : Current limiter reference voltage Z : MR pulse per round [V/rad/s] [N*m] [V] [P/R]
15
HA13609ANT
Set C3 and derive the integration constants from following formulas. R6 = 0 1 R3 = P * C3 R5 = C4 = R3 G(E)
1 2 * R5 * o R7 = R5 Next, determine R4 to match the phase of PLL OUT. (3.46 - VP) R3 R4 = (VP - 1.2) - (1.9 - VP) * R3 / R5 Here, VP : See the electrical characteristics. When log P/ M is greater than 2, a phase advance to compensate for this phenomenon is required. Use the following formula to set the phase advance; C5 * R8 > 20 * 2 P R4 DIS R6 R7 R8 PLL C4 R5 C5 4. The following formulas determine the stuck rotor protect detection time t LP (detects the current limiter operating time), the output off time t OFF, and the setup time tset. The figures show the operating waveforms. tLP = V1 * C105 0.09 x 106 * C105 [sec] Isink V2 tOFF = * C105 0.32 x 106 * C105 [sec] Isource V tset = LH2 * C105 0.0005 x 106 * C105 [sec] Is See the electrical characteristics for the definitions of V1, V2, Isink, Isource, and Is. Standby (MD0k to 2 = Low) Enable Current limiter operation IRNF 0
Lock VLH1 protect VLH2 pin VLL 0 tset
V1 V2 tLP tOFF Output off tLP
Note that a capacitor with a leakage current sufficiently smaller that Isource must be used for C105.
16
HA13609ANT
5. The PWM carrier frequency fPWM is determined by the following formula: 1 [Hz] fPWM = 0.0489 C106 * R1 6. The relationships between the crystal oscillator frequency fOSC and the speed command clock f CLK , the speed detection signal fMR, and the discriminator resolution (number of counts) C are shown below. f CLK = fMR*D1 f OSC = fCLK *1 / D2*C [Hz] However, C must be in the range 1024 C 4095 Here, D1 : The MR signal divisor determined by D1 select D2 : The crystal oscillator frequency divisor determined by D2 select. Configuration of the speed control and phase control blocks when @MD9 = 0 Buffer amplifier fMR'
Speed signal fMR
D1
16 C3 R3
SPEED CLK fCLK
-+ CLK counter Discriminator counter setting
X'tal fOSC
D2
Discriminator (1024 to 4095)
Charge pump
15 R7 19 4Icp R1
PLL PLL SEL
Discriminator
Vp
Discriminator output 14 4% pulse R4 PLL output 13 R5
R6 C4
Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit.
17
HA13609ANT
Timing in phase control mode
fMR' A 3.6 V Discriminator output 0V A
ACC
ACC
A x 4%
ACC
A x 4%
ACC
3.6 V PLL output 1.85 V 0V
ACC ACC
DEC
DEC
Vo
Integrator output
Configuration of the speed control block when @MD9 = 1 fMR' Buffer amplifier
Speed signal fMR SPEED CLK fCLK
D1
CLK counter Discriminator counter setting Discriminator (1024 to 4095) Charge pump R1 19 4Icp R1 16 C2 R2 C1
X'tal fOSC
D2
Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit.
18
HA13609ANT
7. The table below lists reference values for the stabilization capacitors C103 and C104 for the crystal oscillator element according to the frequency used. X'tal (MHz) 4 to 6 6 to 8 C103, C104 (pF) 20 to 40 10 to 20
Use a resonance resistance of under 50 as a criterion for selecting the crystal element used. 8. Include these components if required. 9. The cutoff frequency of the filter formed by C110 and R121 should be between 3 and 10 times the PWM oscillator frequency. 10. The gain, GCTL, from the error amplifier input to RNF is given be the following formula: Rif GCTL = 1 + R125 11. The formulas below determine the relationship between capacitor C108, which sets the power on reset (POR) delay time, and the resistors R126 and R127, which set LVI. R126 [V] VLVI = VSD 1 + R127 However, V LVI > 3V VHYS = R126 * IHYS However, V LVI - VHYS > 2.5V t POR = 0.052 x 10 6 * C108 [sec] The time t POR is the time required for the oscillator to reach stability. This time should be 20ms or longer.
VHYS VLVI VSS < 2.0 V
0V 2.0 V 1.3 V
[V]
VSD, IHYS: See the electrical characteristics.
POR
0V
tPOR RST
tPOR
0V
When using an external reset input to set the IC to the standby state, pin 20 must be set to a low level that is under 0.4V. 12. When the Hall inputs are common mode input, the open circuit protection circuit makes the output transistors non-operational. When all the Hall input phases are open, the lower side output transistors become non-operational. The output transistors will be disabled if one or two phases are disconnected (become open) only when the Hall inputs are common mode.
19
HA13609ANT
13. When setting up the current limiter filter consisting of R120 and C107, R120 should be 4.7k or larger, and C107 and R120 should function as a filter for the recovery current. This filter masks the recovery current due to internal circuits for the current limiter input (pin 26) and the C107 discharge operation determines the PWM off time (by making the current limiter input a low impedance). See the figures. 1/fPWM ON Output (U to W) ON
VRNF
C107 discharge tMASK Current limiter input voltage (pin 26) 0V For recovery current masking: tMASK = 48 64 to fosc fosc @MD8 = 1 24 32 to fosc fosc @MD8 = 0 [SEC] tMASK
tMASK =
[SEC]
14. Use the formula below as a guideline for determining the values of R103, R104, and R122 to R124 when a Hall IC is used. R103 // R104 = R122 to R124 < 20k 15. Take the current limiter input current (see the electrical characteristics) into consideration when determining the values for R106 and R107. 16. Determine the values of R108 to R119 based on the characteristics of the output power transistors used and the output driver characteristics (see the electrical characteristics). 17. Design the wiring in applications so that the potential of the pin 11 ground (the small-signal ground) does not become higher than that of the pin 30 ground (the output stage ground) as shown in the figure. VSS 11 30
20
HA13609ANT
Absolute Maximum Ratings
Item Power-supply voltage Symbol VSS VPS Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature VIN Vout Iout PT Topr Tstg Rated Value 5.5 VSS to 50 VSS 50 30 0.8 -20 to 70 -55 to +125 Unit V V V V mA W C C Note 1 2 3 4 5
Notes: 1. A surge voltage of 6.0V is allowed for up to 10ms. Note that the operating range is as follows: VSS = 4.25 to 5.5V 2. The maximum is VSS if bipolar transistors are used as the output transistors. The maximum is 50 V if bipolar transistors are used as the output transistors. 3. Applies to the logic input pins 1, 2, 3, 5, and 9, and to the analog input pins 17, 20, 24, 26 to 29, and 37 to 42. 4. Applies to the output pins 32, 34, and 36, and to pin 7, the monitor output pin. 5. Applies to the output pins 31 to 36. The maximum value for the monitor output pin is 10mA.
21
HA13609ANT
Electrical Characteristics
Item Current drain Symbol ISSO ISS IPSO IPS Min -- -- -- -- Typ 3.0 15 0.13 2.5 Max 6.5 25 0.5 3.5 Unit mA mA mA mA Test Condition MD0 to 2 = 0, VSS = 5.5V MD0 to 2 = 1, VSS = 5.5V MD0 to 2 = 0, VPS = 50V MD0 to 2 = 1, no load, VPS = 50V 1 to 3, 5, 9 25 6 Applicable Pins 21 Notes 6
Logic inputs
Input lowlevel current Input highlevel current Input lowlevel voltage Input highlevel voltage Clock frequency
IIL IIH VIL VIH fCLK VOH1 VOL1 Rh Vh
-- -- -- 3.5 4 3.5 -- -- 1.5
-50 0 -- -- -- 4.6 0.25 10 --
-100 10 1.5 -- 20 -- 0.4 25% VSS-1.5
A A V V MHz V V k V IOH = 0.5mA IOL= 0.5mA
9 4, 6, 8, 10
Logic outputs
Output highlevel voltage Output lowlevel voltage
Hall amplifier
Input resistance Commonmode input voltage range Differentialmode input voltage range Hysteresis
37 to 42
Vd
70
--
VSS/2
mV
VHYS VOH2 VOH2 VOH2
-- VPS-1.8 10 5.5
40 VPS-1.6 12.5 9.0
-- -- 15 --
mV V V V
Rh = 400 IOH = 20mA, VPS = VSS IOH = 1mA, VPS = 24V IOH = 1mA, VPS = 12V 31, 33, 35
1, 2
Output drivers
Output highlevel voltage
22
HA13609ANT
Electrical Characteristics (cont)
Item Output drivers Output leakage current Output lowlevel voltage Output response time Symbol ILEAK VOL2 TPHI TPLH PWM oscillator and PWM comparator Oscillator lowlevel voltage Oscillator highlevel voltage Oscillator frequency range Oscillator frequency precision Comparator hysteresis Current limiter Input current Offset voltage Speed detection amplifier Common-mode input voltage range Differentialmode input voltage range Gain Input current VL Min -- -- -- -- -- Typ -- 0.15 -- -- 1.1 Max 100 0.3 1.0 1.0 10% Unit A V s s V 12 Test Condition VOH1 = 50V IOL = 20mA IO = 10mA Applicable Pins 32, 34, 36 31 to 36 3 Notes
VH
--
2.8
10%
V
fPWM
2
--
30
kHz
2
ferr1
--
7.7
10%
kHz
fPWM x 1, R1 = 6.2k, C106 = 1000pF 2 Vi = 0 to 2V Vi = 0.5 to 2V 24, 26 26 28, 29
VPHYS IIN1 VOFF VCM
-- -- -15 1.5
50 -- -25 --
-- 10 -40 VSS -1.5 VSS
mV A mV V
VDIFF
60
--
mVP-P
Gain IIN2 I28 I29
-- -- -146 -67 1.45 15
32 -- -95 -53 -- --
-- 20 -62 -39 2.25 --
dB A A A -- mV
f = 1kHz Vi = 1.4V Vi = 0V Vi = 0V I28 / I29 6
2
Input current ratio Input sensitivity
Iratio VS
2
23
HA13609ANT
Electrical Characteristics (cont)
Item Clock oscillator Oscillator frequency range Oscillator frequency precision Program -mable discriminator Count range Operating frequency Count error Charge pump R1 voltage Charge current Discharge current Current ratio Leakage current Clamp voltage Digital ready Precharge Buffer amplifier Lock range manufacturing variation Clamp voltage (1) Internal reference voltage Output resistance Maximum output voltage Voltage gain Error amplifier Input current Offset voltage Voltage gain Gain-bandwidth product Feedback resistance Symbol fosc ferr2 Min 4 -- Typ -- -- Max -- 0.01 Unit MHz % Test Condition X'tal X'tal = 8MHz Applicable Pins 9, 10 2 Notes
N fdis DC VR1 ICP+ ICP- ICP+/ICP- Ioff1 Vclamp N
1024 -- 0 -- -- -- 0.8 -- 2.8 --
-- -- -- 1.16 190 190 1.0 -- 3.0 --
4095 20 1LSB 10% 10% 10% 1.2 100 -- 25
Count MHz -- V A A -- nA V % Vi = 1.5V R1 = 1.5k R1 = 1.5k, Vo = 2.0V
14, 16 4
19 16
7
Vcp(1) Vref
-- --
Vp 1.15
10% 10%
V V
16 16
Ro VB(MAX) GB IIN3 Voff Ge Be Rif
9.8 -- -8 -- -- -- -- --
14 0.7 -6 -- -25 60 0.1 40
18.2 10% -4 150 -50 -- -- 25%
k V dB nA mV dB MHz k VSS = 5V Vi = 2.5V Vi = 1.5V
18
17, 27
2 2
24
HA13609ANT
Electrical Characteristics (cont)
Item Integrating amplifier Internal reference voltage Internal reference voltage difference Input current Output voltage Symbol Vp Min -- Typ 2.2 Max 10% Unit V Test Condition DD6 to 8 = 0 Applicable Pins 15, 16 Notes
Vp
--
2.2+Vp
10%
V
IIN4 VOH3 VOL3
-- 2.75 -- -- --
-- 3.0 -- 60 0.3
250 -- 0.9 -- --
nA V V dB MHz
Vi = 1.5V Io = 0.5mA Io = 0.5mA Vi = 2.5V 2 2
Voltage gain Gainbandwidth product PLL and offset discriminator output Monitor output Output highlevel voltage Output lowlevel voltage Output leakage current Output lowlevel voltage Stuck rotor protector Minimum detection time Output off time High-level voltage Low-level voltage Potential difference Detection-time sink current Output off source current Standby-mode source current
GI BI
VOH4 VOL4
-- --
3.6 0.1
10% 0.2
V V
Io = 0.1mA
13, 14
ILEAK2 VOL5 tLP
-- -- --
-- 0.2 40
50 0.4 25%
A V ms
VOH = 50V IOL = 10mA C105 = 0.47F
7
23
2
tOFF VLH1 VLH2 VLL V1 V2 ISINK ISource IS
-- 3.0 2.5 -- -- -- -- -- --
165 3.2 2.7 1.4 1.9 1.35 25 5.0 4.7
25% -- -- 1.6 10% 10% 30% 30% 35%
ms V V V V V A A mA VLH1-VLL VLH2-VLL Pin 23 voltage = 2.5V Pin 23 voltage = 2.5V Pin 23 voltage = VLH 2
25
HA13609ANT
Electrical Characteristics (cont)
Item LVI Internal reference voltage Hysteresis current Output voltage maintained range P.O.R Delay time Symbol Vsd IHYS VLV tPOR Min 1.13 -- 2.0 -- Typ 1.21 50 -- 24.5 Max 1.29 25% -- 25% Unit V A V ms C108 = 0.47F 21 8, 22 Test Condition Turn on Applicable Pins 20 Notes
Notes: 1. Timing chart 2. Design target values. These are not tested at delivery time. 3. The figure below stipulates the output response time. This is not tested at delivery time. 90% 10% TPLH TPHL
4. Stipulated at the discriminator input frequency. 5. See the timing charts. 6. Stipulated at conditions in which the OSC input is fixed.
26
HA13609ANT
Reference Data
Current Drain vs. Supply Voltage 30
Tj = 25C
Current Drain vs. Supply Voltage 4
Tj = 25C
Current Drain ISS, ISSO (mA)
Current Drain IPS, IPSO (mA)
3
IPS
20
2
ISS
10
1
IPSO
ISSO
0 0 1.5 2.5 3.5 4.5 5.5 Supply Voltage VSS (V)
0
0
10
20
30
40
50
Supply Voltage VPS (V)
Output Driver Low-Level Voltage vs. Output Current Output Driver High-Level Voltage VOH (V) Output Driver Low-Level Voltage VOL (V) 0.4
25 C
Output Driver High-Level Voltage vs. Output Current 15
Tj = 125C Tj = 25C
0.3
Tj
=
1
VPS = 50 V
10
Tj = -20C
0.2
Tj
5C =2
0.1
Tj =
C -20
5
Tj = 125C
Tj = 25C
VPS = 50 V Tj = -20C
0 0 10 20 30 Output Current IO (mA)
0 0 10 20 30 Output Current IO (mA)
27
HA13609ANT
PWM Frequency vs. Junction Temperature 10.0 PWM Frequency fPWM (kHz)
C106 = 1000 pF R1 = 6.2 k fPWM x 1
R1 Voltage vs. Junction Temperature 1.4
R1 = 6.2 k
8.0
R1 Voltage VR1 (V) 10 40 70 100 125
9.0
1.3
1.2
7.0
1.1
-20
-20
10
40
70
100
125
Junction Temperature Tj (C)
Junction Temperature Tj (C)
Error Amplifier Rif vs. Junction Temperature 70 Integrator Reference Voltage VP (V) 2.4
Integrator vs. Junction Temperature
Error Amplifier Rif (k)
60
2.3
50
2.2
40
2.1
30
2.0
-20
10
40
70
100
125
-20
10
40
70
100
125
Junction Temperature Tj (C)
Junction Temperature Tj (C)
28
HA13609ANT
Monitor Output vs. Output Current 0.4 Lock Protector tLP, tOFF (ms) 300 Lock Protector vs. Junction Temperature
C105 = 0.47
Monitor Output VOL (V)
0.3
T 1 j= 25
C
200
tOFF
0.2
Tj = C 25
100
0.1
Tj =
C -20
tLP
0 0 2 4 6 8 10 Output Current IO (mA)
0 -20
10
40
70
100
125
Junction Temperature Tj (C)
LVI Reference Voltage vs. Junction Temperature 1.4 LVI Reference Voltage VSD (V) 30
POR Delay Time vs. Junction Temperature
C108 = 0.47
1.3
POR Delay Time tPOR (ms) 10 40 70 100 125
25
1.2
20
1.1
15
-20
-20
10
40
70
100
125
Junction Temperature Tj (C)
Junction Temperature Tj (C)
29
HA13609ANT
Package Dimensions
Unit: mm
42
37.34 38.0 Max
22 13.4 14.6 Max
1.27 Max
2.54 Min 5.10 Max
1 0.89
1.0
21
15.24
0.10 0.25 + 0.05 -
1.78 0.25
0.48 0.10
0.51 Min
1 - 13
Hitachi Code JEDEC Code EIAJ Code Weight DP-42SA -- SC-551-42 4.42 g
30
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

▲Up To Search▲

Price & Availability of HA13609ANT

	To Download HA13609ANT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .